The fdc file has a Tcl section and other sections that match the tabs in the SCOPE editor (see FDC SCOPE Tabs, on page 11). This table summarizes the syntax formats used in the fdc file:
The FDC non-timing design constraints are the same as the legacy Synplify-style design constraints. The timing constraints are a subset of the Synopsys standard timing constraints, along with some FPGA-specific exten-sions.
All rights reserved.Ĥ FDC and SDC Timing ConstraintsFDC File DescriptionįDC constraints include timing and non-timing design constraints. See Migrating Existing Constraints to FDC, on page 5 for details. The following figure summarizes the methods.Īfter running the sdc2fdc command to generate an fdc file, use the SCOPE editor or a text file editor to check the translated constraints and edit as needed. Generating an FDC FileTo generate the new fdc file, you can translate existing constraints or enter new constraints in the SCOPE editor. Vendor support, starting with Altera TimeQuest in Quartus and Xilinx Vivado for Virtex-7 Easier prototyping of ASIC designs as FPGAs. Sharing of the same ASIC-style timing constraints across FPGA and ASIC tools. The FDC file offers the following advantages: Use this file in place of both the Synopsys standard and the Synplify-style legacy sdc constraint files. It intro-duces a single file that consolidates both timing and non-timing constraints, called the FPGA Design Constraints (fdc) file. All rights reserved.ģ FDC and SDC Timing ConstraintsNew FDC Constraint FileThe G-2012.09 release eliminates the confusion of multiple timing constraint formats. The following figure shows the two constraint scheme choices in previous releases, and the formats of the resulting constraints:Copyright 2012 Synopsys, Inc. You had a choice between using the legacy Synplify-style format for both timing and design constraints, or using a combi-nation of Synopsys standard timing constraints along with Synplify-style design constraints. In releases prior to G-2012.09, this meant that there were two mutually exclusive schemes for specifying constraints, based on the timing constraint format used. These non-timing design constraints are always specified with the same syntax, regardless of the selected timing constraint format. Design constraints are non-timing constraints for FPGA synthesis they include attributes (design_attribute constraints) and physical constraints. In addition, the FPGA synthesis tools honor design constraints. Typical constraints: define_clock, define_input_delay, define_false_path. Synplify legacy timing constraints (sdc) Constraint format native to the Synplify tools. Typical constraints: create_clock, set_input_delay, set_false_path Synopsys standard timing constraints (sdc) Public domain Design Compiler constraints, as defined in the Synopsys SDC Standard. Old Constraint Formats, on page 2 New FDC Constraint File, on page 3 Migrating Existing Constraints to FDC, on page 5 Details of Constraint Conversion, on page 7 Specifying Constraints in the SCOPE Editor, on page 10 FDC SCOPE Tabs, on page 11 Mixed Timing Constraints and Precedence, on page 16Ģ FDC and SDC Timing ConstraintsOld Constraint FormatsIn releases before G-2012.09, there were two parallel, mutually exclusive formats for specifying timing constraints, both of which used the sdc abbreviation and file extension: This document reviews the different formats used in the past, as well as the new approach to defining constraints with a single consolidated file. FDC and SDC Timing ConstraintsSynopsys Application Note, November 2012īeginning with the G-2012.09 release, the Synopsys Synplify family of FPGA synthesis tools uses a new consolidated scheme for handling constraints.
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